A pulser is a circuit that creates a pulse used to clock a latch and allow the latch to behave similar to an edge triggered, flip-flop. Pulser circuits are commonly designed to provide a specified pulse width in order to ensure that a latch coupled to the pulser reliably captures a data value over a desired range of process, voltage and temperature (PVT) variations (also referred to as corners).
An exemplary pulser 100 is illustrated in FIG. 1. The pulser 100 includes a pulse generation circuit 102 (in this instance, a NAND gate coupled to an inverter) and a delay chain 104 (in this instance a NAND gate followed by two inverters). A clock input 110 is coupled to both the pulse generation circuit 102 and the delay chain 104. An early enable input 112 is coupled to the NAND gate of the delay chain 104, and a late enable 114 is coupled to the NAND gate of the pulse generation circuit 102. When the pulser 100 is enabled by both the early enable input 112 and late enable input 114, the pulser 100 produces an output pulse 116 in response to the clock input 110. Either the early enable input 112 or the late enable input 114 may disable pulse generation under certain conditions, depending on timing constraints and other considerations.
In pulser designs, it is desirable that the pulse width provided by the pulser track the pulse width required to write the internal storage node of the latch across PVT corners. The delay chain 104 illustrated in FIG. 1 may not accurately track latch behavior across all PVT corners because the topology of the delay chain 104 is significantly different that the topology of the latch to which it is coupled. In this context, topology refers to the type of circuits and load capacitances in a particular circuit path. For example, the topology of the delay chain 104 includes a NAND gate and two inverters (mainly gate capacitance) whereas the topology of the latch may include a pass gate (mainly diffusion capacitance) and a storage element (mainly gate capacitance). To compensate for the difference in topology, the pulser 100 may be designed to provide a wider pulse 116 than is needed to write the latch at favorable PVT corners in order to guarantee writability of the latch at unfavorable PVT corners (for example, corners where P-type transistors (PMOS devices) are slow and N-type transistors (NMOS devices) are fast or vice versa). Although using a wider pulse allows for more robust pulse generation at unfavorable PVT corners, it may create hold-time issues in favorable PVT corners. Additionally, because the delay chain 104 may track differently across the PVT corners than the NAND gate of the pulse generation circuit 102, it is even possible that the pulse 116 may fail to be generated at all in some unfavorable PVT corners.
Lengthening the pulse in the case of the design illustrated in FIG. 1 may involve the addition of extra inverters to the delay chain 104, which increases the area and power consumption of the overall design. The location of a pulse enable input within the pulser circuit may also involve design tradeoffs. An early pulse enable may allow theoretically greater power savings but be difficult to use from a timing perspective, whereas a late pulse enable may be easier to use from a timing perspective but may provide less favorable power savings. For example, as can be seen in the exemplary pulser of FIG. 1, even when the pulser is disabled via the late enable 114, the entire delay chain 104 will still switch every clock cycle.